The new report_eco_sequence command logs every change made during incremental synthesis, allowing for transparent late-stage modifications without breaking functional equivalence.
Save this as run_synthesis.tcl and execute with dc_shell -f run_synthesis.tcl. synopsys design compiler tutorial 2021
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# Synopsys DC 2021 Tutorial Script
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set my_design "riscv_core"
report_timing > reports/$my_design.timing
report_area > reports/$my_design.area The new report_eco_sequence command logs every change made